1. Field of the Invention
The present invention relates to an ESD (electrostatic discharge) protection circuit for protecting an internal circuit from ESD.
2. Description of Related Art
In recent years, the improvement of reliability of a semiconductor device has been required in various fields. For example, in particular, high reliability is required in the semiconductor device used in a product affecting human life due to a fault as in driver circuits for a vehicle-mounted car navigation system and a medical liquid crystal monitor. In order to realize high reliability in these products, it is necessary to increase a resistance to an overvoltage (or ESD) from the outside. More specifically, the semiconductor device with high ESD resistance has been demanded.
A conventional technique for enhancing ESD resistance in LSI (Large Scale Integrated circuit) include a protection circuit (i.e. ESD protection circuit) arranged in the periphery of an LSI chip. The ESD protection circuit prevents an internal element (or internal circuit) of LSI from being destroyed by changing a current path of ESD inputted from the outside.
FIG. 1 shows an example of an equivalent circuit of LSI (or semiconductor device) provided with an ESD protection circuit and a power supply protection circuit. Referring to FIG. 1, the LSI includes an input/output pad 101 for inputting/outputting an external signal, a VDD interconnection 102 to be connected to a higher power supply VDD, a VSS interconnection 103 to be connected to a lower power supply VSS, an ESD protection circuit 110, a power supply protection circuit 120, and an internal circuit 130.
The ESD protection circuit 110 is provided with a PNP bipolar transistor 121 which is connected to the input/output pad 101, and a parasitic diode 122. The PNP bipolar transistor 121 has an emitter (E) connected to the input/output pad 101, a base (B) connected to the VDD interconnection 102 (i.e. higher power supply VDD), and a collector (C) connected to the VSS interconnection 103 (i.e. lower power supply VSS). The parasitic diode 122 also has an anode (A) connected to the input/output pad 101, and a cathode (K) connected to the VDD interconnection 102 (i.e. higher power supply VDD).
The power supply protection circuit 120 has a diode with an anode (A) connected to the lower power supply VSS and a cathode (K) connected to the higher power supply VDD. When an ESD voltage is applied between the VDD interconnection 102 and the VSS interconnection 103, an ESD current flows in the power supply protection circuit 120 to protect the internal circuit 130.
The ESD protection circuit according to a conventional technique is disclosed in Japanese Patent Application Publication Nos. JP-A-Heisei 10-223846 (related art 1), JP-P2001-223277A (related art 2), and JP-P2000-269440A (related art 3).
The ESD protection circuit 110 in the conventional technique will be described with reference to FIGS. 2 and 3. FIG. 2 is a plan view showing a layout example of the ESD protection circuit according to the conventional technique, and FIG. 3 is a cross-sectional view showing a cross-sectional structure of a semiconductor device along a line A-A′ of FIG. 2. It should be noted that the VDD interconnection 102, an interconnection to be connected to the input/output pad 101, and the VSS interconnection 103 are omitted in FIG. 2.
The ESD protection circuit 110 in the conventional technique includes an N-type well 112 formed in the surface region of a P-type substrate 111 in a Z axis direction, in addition to an element isolation region 113, P+-diffusion layers 114A and 114B, and N+-diffusion layers 115, which are formed in the N-type well 112. The N+-diffusion layer 115 is connected to the VDD interconnection 102 via a contact 116. The P+-diffusion layer 114A is connected to the input/output pad 101 via a contact 117. The P+-diffusion layer 114B is connected to the VSS interconnection 103 via a contact 118. The element isolation region 113 is exemplified by a field oxide film and is provided in a space interposed among the P+-diffusion layers 114A and 114B and the N+-diffusion layers 115. The element isolation region 113 is formed by LOCOS (Local Oxidation of Silicon) or STI (Shallow Trench Isolation).
By employing such a structure, the PNP bipolar transistor 121 is formed by using the P+-diffusion layer 114A as an emitter (E), the P+-diffusion layer 114B as a collector (C) and the N+-diffusion layer 115 as a base (B). The P+-diffusion layer 114A and the N-type well 112 also constitute a parasitic diode 122.
Here, if plus static electricity with a higher potential than the higher power supply VDD is applied to the input/output pad 101 due to the ESD, a snap-back operation of the PNP bipolar transistor 121 allows an overcurrent (i.e. ESD current) to flow from the P+-diffusion layer 114A connected to the input/output pad 101 to the P+-diffusion layer 114B connected to the VSS interconnection 103. This overcurrent flows through the PNP bipolar transistor 121 to protect the internal circuit 130. In contrast, if minus static electricity with a lower potential than the lower power supply VSS is applied to the input/output pad 101, a breakdown operation of the parasitic diode 122 to the PNP bipolar transistor 121 allows an overcurrent (i.e. ESD current) to flow from the N+-diffusion layer 115 connected to the VDD interconnection 102 to the P+-diffusion layer 114A connected to the input/output pad 101. Thus, the internal circuit 130 is protected from the ESD current.
FIG. 4 is a conceptual diagram showing a current density of the ESD current flowing into the P+-diffusion layer 114A when minus static electricity is applied to the input/output pad 101. When the minus static electricity is applied to the input/output pad 101, the ESD current flows into the P+-diffusion layer 114A via a region opposing to the N+-diffusion layer 115 (i.e. region shown as the width W10 in FIG. 4). Referring to FIG. 4, the width W10 of the P+-diffusion layer 114A opposing to the N+-diffusion layer 115 is extremely narrower than the width W20 of the N+-diffusion layer 115. Therefore, a current density of the ESD current in the region of the width W10 of the P+-diffusion layer 114A is larger, and accordingly the P+-diffusion layer 114A may be destroyed. That is, in the ESD protection circuit in the conventional technique, ESD resistance is very low with respect to minus static electricity.